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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT670 4 x 4 register file; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4 x 4 register file; 3-state FEATURES * Simultaneous and independent read and write operations * Expandable to almost any word size and bit length * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT670 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT670 are 16-bit 3-state register files organized as 4 words of 4 bits each. Separated read and write address inputs (RA, RB and WA, WB) and enable inputs (RE and WE) are available, permitting simultaneous writing into one word location and reading from another location. The 4-bit word to be stored is presented to four data inputs (D0 to D3). The WA and WB inputs determine QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT670 the location of the stored word. When the WE input is LOW, the data is entered into the addressed location. The addressed location remains transparent to the data while the WE input is LOW. Data supplied at the inputs will be read out in true (non-inverting) form from the 3-state outputs (Q0 to Q3). Dn and Wn inputs are inhibited when WE is HIGH. Direct acquisition of data stored in any of the four registers is made possible by individual read address inputs (RA and RB). The addressed word appears at the four outputs when the RE is LOW. Data outputs are in the high impedance OFF-state when RE is HIGH. This permits outputs to be tied together to increase the word capacity to very large numbers. Design of the read enable signals for the stacked devices must ensure that there is no overlap in the LOW levels which would cause more than one output to be active at the same time. Parallel expansion to generate n-bit words is accomplished by driving the enable and address inputs of each device in parallel. TYPICAL SYMBOL PARAMETER tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC -1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". where: propagation delay Dn to Qn input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 23 3.5 122 HCT 23 3.5 124 ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification 4 x 4 register file; 3-state PIN DESCRIPTION PIN NO. 5, 4 8 10, 9, 7, 6 11 12 14, 13 15, 1, 2, 3 16 SYMBOL RA, RB GND Q0 to Q3 RE WE WA, WB D0 to D3 VCC NAME AND FUNCTION read address inputs ground (0 V) data outputs 3-state output read enable input (active LOW) write enable input (active LOW) write address inputs data inputs positive supply voltage 74HC/HCT670 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. WRITE MODE SELECT TABLE OPERATING MODE write data data latched Note 1. The write address (WA and WB) to the "internal latches" must be stable while WE is LOW for conventional operation. INPUTS WE L L H Dn L H X INTERNAL LATCHES(1) L H no change READ MODE SELECT TABLE OPERATING MODE read disabled Notes 1. The selection of the "internal latches" by read address (RA and RB) are not constrained by WE or RE operation. H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state 3 INPUTS RE L L H INTERNAL LATCHES(1) L H X OUTPUT Qn L H Z December 1990 Philips Semiconductors Product specification 4 x 4 register file; 3-state 74HC/HCT670 Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 4 x 4 register file; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to+125 max. 295 59 50 375 75 64 375 75 64 225 45 38 225 45 38 90 18 15 120 24 20 90 18 15 90 18 15 5 5 5 5 5 5 150 30 26 ns 74HC/HCT670 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 min. typ. max. min. max. min. tPHL/ tPLH propagation delay RA, RB to Qn propagation delay WE to Qn propagation delay Dn to Qn 3-state output enable time RE to Qn 3-state output disable time RE to Qn output transition time 58 21 17 77 28 22 74 27 22 39 14 11 47 17 14 14 5 4 80 16 14 60 12 10 60 12 10 5 5 5 5 5 5 100 20 17 14 5 4 3 1 1 6 2 2 0 0 0 0 0 0 28 10 8 5 195 39 33 250 50 43 250 50 43 150 30 26 150 30 26 60 12 10 100 20 17 75 15 13 75 15 13 5 5 5 5 5 5 125 25 21 245 49 42 315 63 54 315 63 54 190 38 33 190 38 33 75 15 13 tPHL/ tPLH ns Fig.7 tPHL/ tPLH ns Fig.7 tPZH/ tPZL ns Fig.9 tPHZ/ tPLZ ns Fig.9 tTHL/ tTLH ns Fig.6 tW write enable pulse width LOW set-up time Dn to WE set-up time WA, WB to WE hold time Dn to WE hold time WA, WB to WE latch time WE to RA, RB ns Fig.8 tsu ns Fig.8 tsu ns Fig.8 th ns Fig.8 th ns Fig.8 tlatch ns Fig.8 December 1990 Philips Semiconductors Product specification 4 x 4 register file; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT670 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn WE, WA WB RA RB RE UNIT LOAD COEFFICIENT 0.25 0.40 0.60 0.70 1.10 1.35 December 1990 6 Philips Semiconductors Product specification 4 x 4 register file; 3-state AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 60 75 75 53 53 18 27 18 18 5 5 38 ns ns ns ns ns ns ns ns ns ns ns ns 74HC/HCT670 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.7 Fig.9 Fig.9 Fig.6 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 min. typ. max. min. max. min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu tsu th th tlatch propagation delay RA, RB to Qn propagation delay WE to Qn propagation delay Dn to Qn 3-state output enable time RE to Qn 3-state output disable time RE to Qn output transition time write enable pulse width LOW set-up time Dn to WE set-up time WA, WB to WE hold time Dn to WE hold time WA, WB to WE latch time WE to RA, RB 18 12 12 5 5 25 21 28 27 18 19 5 9 4 -2 -1 0 11 40 50 50 35 35 12 23 15 15 5 5 31 50 63 63 44 44 15 December 1990 7 Philips Semiconductors Product specification 4 x 4 register file; 3-state AC WAVEFORMS 74HC/HCT670 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the read address input (RA, RB) to output (Qn) propagation delays and output transition times. Fig.7 Waveforms showing the write enable input (WE) and data input (Dn) to output (Qn) propagation delays, and the write enable pulse width. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. The time allowed for the internal output of the latch to assume the state of the new data (tlatch) is important only when attempting to read from a location immediately after that location has received new data. This parameter is measured from the falling edge of WE to the rising edge of RA or RB, RE must be LOW. Fig.8 Waveforms showing the write address input (WA, WB) and data input (Dn) to write enable (WE) set-up, hold and latch times. December 1990 8 Philips Semiconductors Product specification 4 x 4 register file; 3-state 74HC/HCT670 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the read enable (RE) to output (Qn) enable and disable times, and the read enable pulse width. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 9 |
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